A·ru·nạ

A·ru·nạ

Assistant Professor | Engineer | Researcher | Automotive Enthusiast

Projects

Automatic Implementation of Secure Silicon (AISS)

The Automatic Implementation of Secure Silicon (AISS) program aims to ease the burden of developing secure chips. AISS seeks to create a novel, automated chip design flow that will allow security mechanisms to scale consistently with the goals of a chip design. The target design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security trade-off. The target system on chip (SoC) will be automatically generated, integrated, and optimized, and will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased.

DUO-DE: Surface-Duo Dual Experience

The Surface Duo, Microsoft’s dual-screen Android device, aimed to redefine mobile productivity by offering a unique form factor that combined the versatility of two screens with the familiarity of the Android operating system. Launched in September 2020, the device garnered attention for its innovative design but faced criticism for its high price, software bugs, and lack of 5G support. Despite a subsequent release of the Surface Duo 2 in October 2021, which addressed some of these issues with improved hardware and features, the devices struggled to gain significant market traction. Microsoft officially ceased updates and support for the Surface Duo line in early 2023, marking the end of its interest in the dual-screen smartphone market. However, with AOSP GSI and the help of the opensource community, we are building the Surface Duo Dual Experience (DUO-DE) custom ROM with over-the-air (OTA) update support.

Depth Map Generation on FPGA

Real Time depth map generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions. Most of the image processing projects in academia has been done on higher-end FPGA’s with a considerable amount of resources. The main objective of this project is to implement a reliable embedded system on a lower end FPGA with limited resources. This project is based on Disparity calculation based on SAD (Sum of Absolute Difference) algorithm and creating a depth map.

Test Vector Leakage Assessment

Test vector leakage assessment evaluates the side-channel leakage of sensitive information from the hardware implementation of a design. While TVLA for symmetric cryptography has been well studied, it is not applicable to asymmetric cryptography algorithms. Asymmetric-key algorithms involve complex computations in multiple stages that can lead to varying trace lengths depending on input parameters and associated constraints. In this article, we design an effective TVLA technique for asymmetric-key cryptosystems that can compare lengthy trace data with a good statistical resolution and generate valid input (test) patterns to satisfy specific constraints. Specifically, this article makes the following major contributions. The proposed test generation algorithm can produce valid test patterns to maximize the power signature differences. Our proposed partition-based differential power analysis can significantly improve the TVLA accuracy.

LFI resistant FSM encoding

Simple Greedy algorithm AREST, which can find you the best state encoding for a given FSM that is resistant against Laser Fault Injection (LFI) attacks. Finite State Machines (FSMs) are widely used to implement complex computation sequences and communication protocols. An FSM may consist of different states with different privilege levels, such as protected and non-protected. Ideally,switching from a non-protected state to a protected state should involve an authorization transition. However, with Laser-based Fault injection (LFI), an attacker can bypass authorization by flipping bits in the FSM’s state vector. In order to mitigate LFI vulnerability, one can encode the FSM states with the objective of maintaining a large Hamming Distance (HD) between each pair of states. The existing FSM encoding algorithms are either very slow, rely on the user’s mathematical ability to manually generate certain state encodings, or lead to unacceptable area overhead.

RoboCat Drone: Robust Flying Project

Design files of the simple heavy lifting drone created for Drone enduarance race Sky of Icarus. The robustness of a quadcopter frame is of paramount importance in ensuring its durability and reliable performance. A well-designed and sturdy frame is built to withstand the rigors of flight, including impacts, vibrations, and other external forces. It is typically constructed from high-quality materials such as carbon fiber or aluminum, which provide excellent strength-to-weight ratios. The frame’s design incorporates reinforcement at critical stress points, such as motor mounts and landing gear attachments, to distribute forces evenly and prevent structural failure.

Realtime Kinematics and NTRIP

Real-Time Kinematics (RTK) GPS is a precise positioning technology that enhances the accuracy of standard GPS systems by utilizing additional information from reference stations. Traditional GPS receivers provide location information with an accuracy ranging from a few meters to several tens of meters. However, RTK GPS offers centimeter-level accuracy by employing a base station that continuously collects data from satellites and transmits correction signals to the rover receiver in real time. These correction signals compensate for atmospheric delays and other error sources, allowing the rover to calculate its position with exceptional precision. RTK GPS finds applications in various industries, including surveying, precision agriculture, construction, and autonomous navigation. Its high accuracy and real-time capabilities enable tasks such as land surveying, machine guidance, and UAV navigation with unparalleled precision, revolutionizing industries that require precise positioning information.

TrojanWars: Hardware Malicious Implant Detection

Hardware trojan detection is a critical process that aims to identify and mitigate the presence of malicious alterations or additions in integrated circuits or electronic devices. It involves various techniques and methodologies to ensure the integrity and trustworthiness of hardware components. Hardware trojans can be inserted during the manufacturing process, and they can pose significant risks by compromising the functionality, security, and reliability of the affected systems. Detection methods range from physical inspections, such as side-channel analysis and optical inspection, to more advanced techniques like hardware fingerprinting, anomaly detection, and formal verification. By employing a combination of these approaches, hardware trojan detection plays a vital role in safeguarding critical infrastructure, preventing unauthorized access, and maintaining the trustworthiness of electronic systems. TrojanWars utilizes efficient test generation-based techniques to activate malicious implants if present in the designs.