Aruna Jayasena is actively engaged in research on systems security and secure computing architectures. His work lies at the intersection of Computer and Electrical Engineering, with a focus on heterogeneous system design, applied cryptography, trusted execution, and hardware-firmware co-validation. Currently, he concentrates on advancing these fields through innovative projects, some of which are publicly available on his GitHub. Throughout his diverse range of projects, Aruna has developed extensive experience with various CAD tools, including Synopsys tools (VCS, DC, TMAX), Yosys Open Source EDA (Yosys, nextpnr, icestorm), Xilinx tools (Vivado, ISE), Intel Quartus, ModelSim, Icarus Verilog, symbolic verification tools (Racket + Rosette + Z3), Altium, Kicad, and Solidworks. Beyond his professional endeavors, Aruna is an avid automotive enthusiast who enjoys working on cars and drones, pushing them to their limits in the field to assess their performance. In his free time, he also indulges in activities such as swimming, kayaking, and exploring the epic world of automobiles.
Education
 | University of Florida 🇺🇸 |
 | University of Moratuwa 🇱🇰 |
Updates
- Our paper, 'FirmWall: Directed Symbolic Execution of Firmware Binaries for Defending against Unauthorized System Calls' in IEEE Transactions on Information Forensics & Security (TIFS). Kudos to my co-authors. Read more...
- Our paper 'Information Leakage through Physical Layer Supply Voltage Coupling Vulnerability' was accepted in IEEE TVLSI! Read more...
- Our paper, 'Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes' was accepted in IEEE Transactions on Information Forensics & Security (TIFS). Kudos to my co-authors. Read more...
- I have officially defended my Ph.D. I am joining UTC as an Tenure-Track Assistant Professor in Fall 2025. Read more...
